A TiSi2-Si Schottky diode clamped merged drain (SCMD) CMOS concept is proposed and its initial feasibility is demonstrated by fabricating the structure in foundry 0.8 and 0.5 mum salicide CMOS processes, Output I-V and isolation characteristics of SCMD MOS transistors are almost identical to those of conventional MOS transistors, while the current gains of parasitic n(-)-drain/p-substrate/n-well and p(+) -drain/n-well/p-substrate bipolar transistors involved in latchup are significantly reduced. This enables a reduction of n(+)-drain-to-p(+)-drain spacing. This reduction in combination with the decreased drain lengths of transistors in the SCMD CMOS structure results in a similar to30% area reduction for an inverter. (C) 2002 Elsevier Science Ltd. All rights reserved.