In this work, we identify polyreoxidation as a process step for selectively thickening the gate oxide at the edges (in the gate overlap region), and hence for suppressing the edge component of direct tunneling through ultrathin gate oxides in NMOSFETs. It is shown that by varying the different polyreoxidation parameters viz: temperature and polyreoxidation time it is possible to achieve different levels of gate oxide edge thickening. This essentially implies that a desired level of gate leakage current may be maintained without modifying the gate oxidation process significantly. (C) 2002 Elsevier Science Ltd. All rights reserved.