N-channel FETs fabricated in SiC by ion implantation are studied by using deep level transient spectroscopy (DLTS) to detect deep levels, which may influence device performance significantly. Enhancement mode MISFETs, made on 6H-SiC p-type epilayer using nitrogen source/drain implantation and MESFETs, made on semi-insulating bulk 4H-SiC using nitrogen as the channel and source/drain implantations were used for the DLTS characterization. For both of these devices, effective channel mobility is much smaller than the bulk mobility, due to possible residual implant lattice damage or dielectric/SiC interface traps. For MESFETs five different traps were identified and characterized by activation energies of 0.51, 0.6, 0.68, 0.768 and 0.89 eV above the valence band edge E,. Five gate dielectric traps and eight interface hole/electron traps were revealed for MISFETs. Gate dielectric traps were distinguished by different activation energies of 0.109, 0.132, 0.15, 0.4 and 0.6 eV. Two shallow gate dielectric/semiconductor interface traps were identified at E-v + 0.2 eV (hole trap) and E-c -0.362 eV (electron trap). Four deep level traps were found in the activation energy range of 0.6-0.8 eV above the valence band edge with capture cross-section similar to10(-16)-10(-17) cm(2). Other traps were detected at DeltaE = 0.437 and 0.47 eV above E-v. (C) 2002 Elsevier Science Ltd. All rights reserved.