Solid-State Electronics, Vol.47, No.4, 661-664, 2003
Process technique for SEU reliability improvement of deep sub-micron SRAM cell
A technique is proposed to improve single event upset reliability of 0.09 mum SRAM cell by introducing an extra implant step similar to pocket halo, super steep retrograde channel and V-t adjust implant steps in the existing process flow. It is shown that by changing the energy, dose and angle of implant, a heavily doped p+ region of high recombination rate can be introduced beneath the source/drain junctions. This results in decrease in effective charge collection volume, thereby increasing critical LET to flip the SRAM cell. (C) 2002 Elsevier Science Ltd. All rights reserved.