The scalability of today's metallization in interconnect technology is demonstrated and nano-interconnects of critical dimension regarding the International Technology Roadmap for Semiconductors (ITRS) roadmap requirements for the 22 nm technology node are shown. Sub-50 nm copper damascene lines were fabricated using an adapted spacer technique with current optical lithography and standard manufacturing equipment for processing 150 or 200 mm-diameter wafers. For comparison an electron beam microscope based lithography was used for direct writing of patterns with narrow pitches. For both methods particular attention will be paid to issues of patterning and adaptation of unit processes as well as metal deposition. Electrical measurements for assessing the fabricated nano-interconnects with respect to the influences of barrier and seed layer thicknesses are shown briefly. The feasibility of interconnects with end-of-roadmap feature sizes demonstrated by these measurements gives reason to expect a bright future of copper interconnect processing technology. (C) 2003 Elsevier Science Ltd. All rights reserved.