Solid-State Electronics, Vol.47, No.9, 1589-1596, 2003
A capacitance-voltage model for polysilicon-gated MOS devices including substrate quantization effects based on modification of the total semiconductor charge
We present a model for simulating the capacitance-voltage (C-V) characteristics of polysilicon-gated MOS devices with thin oxides. The model includes substrate quantization effects through a modification of the total semiconductor charge. Therefore, solutions for C-V can be quickly obtained without the computational burden of solving over a physical grid. The model includes polysilicon depletion by self-consistently solving the charge balance equation. We conclude with comparisons of the C-V characteristics obtained with this model and those obtained by self-consistent solutions to the Schrodinger and Poisson equations. Good agreement was observed over a wide range of oxide thickness (2.0-15.0 nm) and substrate doping (10(15)-10(18) cm(-3)). Published by Elsevier Science Ltd.
Keywords:MOS structure;quantum mechanical effects;MOS model;capacitance-voltage;poly-depletion;thin oxides