Along with the MOSFET feature size shrinking, accurately extracting L-eff becomes increasingly challenge. This letter proposes a new L-eff extraction algorithm for sub-100 nm MOSFET technology which is based on the drain-induced-barrier-lowering (DIBL) effect. Applying this method in sub-100 nm CMOS technology, consistent L-eff results can be obtained below 50 nm. (C) 2003 Elsevier Ltd. All rights reserved.