Ultra-thin-body silicon-on-insulator (UTB-SOI) is one of the most promising candidates for future CMOS technologies with minimum feature sizes below 50 urn. In this paper, we analyse the impact of different combinations of doping profiles and gate sidewall spacer thicknesses on device performance. For this purpose we have simulated fully depleted SOI-MOSFETs with thin undoped silicon bodies using a coupled device and circuit simulation. (C) 2003 Elsevier Ltd. All rights reserved.