Feature size control in deep sub-micron CMOS processes requires attention to the local and global metal density. This can lead to the placement of metal on top of sensitive analogue components. In this study we report the first results on the impact of metal coverage on the matching of high and low ohmic polysilicon resistors in a 0.35 mum analogue CMOS technology. A significant degradation in matching is observed, especially when matched resistors have unequal metal coverage. In contrast to reported results in one earlier other technology, the mismatch degradation is not strongly influenced by process changes such as modified sinter temperature or the presence of titanium in the metallisation. Limited data show that the effect is also seen in bulk silicon resistors, with a larger magnitude. It is demonstrated that the most likely explanation for the effect is the impact of stress from the metal film on the silicon resistance. A consequence of the effect is that in analogue designs metal must be kept a sufficient distance (10 mum in this process) away from matched resistor pairs. (C) 2003 Published by Elsevier Ltd.