화학공학소재연구정보센터
Solid-State Electronics, Vol.48, No.5, 813-825, 2004
Noise modeling in fully depleted SOI MOSFETs
In this paper, we are presenting a noise modeling technique in fully depleted (FD) SOI MOSFET. Starting from a physical compact model which allows us to capture the physics in such devices, an original microscopic noise model, suitable to calculate the noise performance of any field effect transistor, is developed. The method is applied to study the noise properties of FD SOI MOSFETs (0.25 mum physical gate length, 0.16 mum effective gate length); this includes a discussion at a microscopic level, the calculation of the usual P, R, C parameters (close to the device physics) and of the noise performances, taking into account extrinsic elements. To conclude, a discussion related to the noise performances as a function of the down-scaling is proposed. (C) 2004 Elsevier Ltd. All rights reserved.