An analytical heat flow model for SOI circuits is presented. The model is able to account for heat exchanges among devices and heat loss from the silicon film and interconnects to the substrate through the buried oxide. The developed model can accurately and efficiently predict the temperature distribution in the interconnect/poly-lines and SOI devices. The model is applied to SOI current mirrors to study heat flow in different layout designs. The results from the developed model are verified with those from Raphael, a 3D numerical simulator that can provide the detailed 3D temperature distribution in interconnect/poly-lines. (C) 2004 Elsevier Ltd. All rights reserved.