The impact of hot-carrier (HQ stress on thin gate oxide PD SOI nMOSFETs is investigated by analyzing the front and back channel current voltage characteristics and the switch-off drain current transients. A particular hot-carrier degradation mode, characterized by a turn-around behavior for front gate threshold voltage degradation, is analyzed for devices with different geometries, bias conditions and source/drain architecture. A significant positive back gate threshold voltage shift is also observed after long HC stress. The maximum hot-carrier degradation (HCD) is obtained for the highest front gate biases, corresponding to the conditions of maximum electron valence band injection of majority carriers into the floating body. The presence of the HCD is found to reduce both the generation and the recombination switch-off drain current transient times. Unbiased thermal annealing in the range of 200-250 degrees C significantly reduces the hot-carrier-induced damage affecting the back channel characteristics. Whereas front gate direct tunnel stress is not causing any significant degradation for stress biases up to about two times the power supply for this technology node and reasonably short stress times, for the highest stress conditions the drain current transients are found to be progressively faster till front gate dielectric breakdown occurs. (c) 2005 Elsevier Ltd. All rights reserved.