High-performance bulk CMOS technology for 65/45 nm nodes is reviewed with respect to on-current enhancing techniques. Through continuous efforts to increase on-current while scaling gate length, required targets for 65/45 nm node will be satisfied. For high-performance application at further nodes, a metal gate and enhanced stress control as well as conventional scaling must be introduced with the least process complexity. (c) 2005 Elsevier Ltd. All rights reserved.