The design, fabrication, and electrical characterization of enhancement-mode HEMTs (E-HEMTs) and depletion-mode HEMTs (D-HEMTs) on a common InP substrate are reported. The integration of E- and D-HEMTs (E/D-HEMTs) is a potentially useful technology for the realization of high-speed, low-power digital circuits. The layer structures for E/D-HEMTs were optimized in terms of the thicknesses of the spacer and Schottky layers and sheet carrier concentration in the channel. The buried-Pt gate technology was utilized to achieve the desired threshold voltages for both 0.15 mu m gate E- and D-HEMTs. The fabricated devices exhibited threshold voltages of -0.3 and 0.1 V, peak transconductance (Gi(m,max)) values that are higher than 1020 and 1050 mS/mm, and the voltages where the peak transconductances occurred (V-gp) were 0.0 and 0.4 V for D- and E-HEMTs, respectively. Unity gain cut-off frequencies (f(T)'s) above 190 and 180 GHz were obtained for D-HEMTs and E-HEMTs, respectively. (c) 2006 Elsevier Ltd. All rights reserved.