Inherently smaller cross-sectional area of heavily doped source/drain regions (HDDs) in multiple gate transistors is known to give rise to a higher contact resistance between Si and HDD silicide as compared to a planar transistor with similar width of the Si channel. In order to characterize the contact resistance, multiple gate FETs have been fabricated with fin widths and gate lengths down to 18 and 45 nm, respectively. Experiments performed by varying layout and technology parameters show that Nickel silicide forms wrapped contacts around HDDs. Further, the silicidation process is shown to be fully siliciding HDDs in devices with narrow fins, where a selective epitaxial growth of Si has been performed in HDDs. (c) 2006 Elsevier Ltd. All rights reserved.