A memory cell consisting of a Pt/VO2/ Pt switch element and a Pt/NiO/Pt memory element connected in series. By applying a voltage higher than V-th of 0.6 V, the switch element reaches the on state and the cell can be accessed. Since reset and set voltages are higher than V-th, information can be written by simply applying an appropriate voltage to a selected cell. By applying a voltage lower than V-th to the other cells, we can keep the other cells in the off state and prevent interference between the selected cell and the others.