The effect of process parameters on blind via formation for vertical interconnects using an STS deep reactive ion etch tool is reported. A modified Bosch process is used to create vias (20 and 25 mu m in diameter) with varying depths and sidewall angles on 125 mm diameter silicon wafers using a photoresist mask. The effect of changing the flow rates of SF6 and C4F8 gases, the automatic pressure control angle, and coil and platen powers on via profile and sidewall morphology is studied. The effect of chamber cleaning and conditioning on controlling the diameter growth at the top surface of the via is also reported. The various via profiles are examined using an environmental scanning electron microscope and by observing via cross sections. Each parameter plays a critical role in obtaining a specified via profile. A sloped via sidewall is required for our application of fabricating vertical interconnects. After etching, vias are insulated by depositing 2 mu m of silicon dioxide by plasma enhanced chemical vapor deposition at 250 degrees C. A barrier film of TaN is reactively sputtered after insulation deposition followed by a Cu sputtered seed film allowing electroplated Cu to fill the via. The sloped via sidewall is required due to the weak step coverage obtained by sputter deposition. (C) 2007 American Vacuum Society.