In this paper, we report a comprehensive study of the gate oxide/channel interface properties of submicron MOSFETs integrated in a SON technology [Jurczak M, et al. Silicon-On-Nothing (SON) - an innovative process for advanced CMOS. IEEE-TED 2000;47:2179, Monfray S, et al. First 80 nm SON (Silicon On Nothing) transistor with perfect morphology and high electrical performance. IEDM Tech Dig 2001:645, Monfray S, et al. SON (Silicon-On-Nothing) technological CMOS platform: Highly performant devices and SRAM cells. IEDM Tech Dig 2004:635]. The interface state density (D-it) is determined by two-levels charge pumping analysis on long-channel partially-SON transistors where the Si-channel is in contact with the substrate. On short-channel SON transistors, where the Si-channel is completely isolated from the substrate, we were able to determine the characteristics of individual trap located inside the gate oxide using random telegraphic signal (RTS) analysis: activation energy and distance from the SiO2/Si interface. The experimental RTS results demonstrate the validity of the Shockley-Read-Hall (SRH) statistics for a single trap activity and conclusively prove that SON technology does not introduce additional defects at the gate oxide/channel interface when compared to CMOS technology. (C) 2007 Elsevier Ltd. All rights reserved.