The contribution from relatively low-K SiON interfacial transition regions (ITRs) between Si and transition metal (TM) gate dielectrics places a significant limitation on equivalent oxide thickness ( EOT) scaling for Si complementary metal-oxide-semiconductor (CMOS) devices. This limitation is equally significant and limiting for Ge CMOS devices. Low-K Ge-based ITRs in Ge devices have also been shown to limit performance and reliability, particular for n-MOS field effect transistors. This article identifies the source of signicant electron trapping at interfaces between n-Ge or inverted p-Ge, and Ge oxide, nitride and oxynitride ITRs. This is shown to be an interfacial band alignment issue in which native Ge ITRs have conduction band offset energies smaller than those of TM dielectrics, and trap electrons for negative Ge substrate bias. This article also describes a novel remote plasma processing approach for effectively eliminating any significant native Ge ITRs and using a plasma-processing/annealing process sequence for bonding TM gate dielectrics directly to the Ge substrate surface. (C) 2008 Elsevier B.V. All rights reserved.