With the continuous scaling down of the critical dimensions (CDs) of semiconductor devices, the linewidth roughness (LWR) becomes a non-negligible parameter that needs to be controlled within 1 nm (at 3 sigma) for the 32 nm node and beyond. In this article, the authors have used a CD-atomic force microscopy to investigate the evolution of the LWR during the subsequent lithography and plasma etching steps involved in the patterning of polysilicon transistor gates. The authors demonstrate that the LWR present on the etching mask [photoresist/bottom antireflective coating (BARC), SiO2 or amorphous carbon hard masks] right before the gate etching is transferred into the polysilicon during the HBr/Cl-2/O-2 gate etching step. Thus, the final polysilicon LWR directly is strongly dependent on the lithography and plasma etching steps preceding the gate etching step. The authors show that by applying plasma treatment to minimize the resist mask LWR prior to all the other etching steps or by optimizing the BARC opening plasma chemistry, the final polysilicon LWR can be minimized. The authors also demonstrate that the introduction of hard masks (SiO2 or amorphous carbon) helps to reduce further the final polysilicon gate LWR. Finally, the authors discuss the role of the ion bombardment in the smoothening/roughening of the pattern sidewalls during plasma processes. (C) 2008 American Vacuum Society.