Although the next generation high-k gate dielectrics has been defined for the 45 nm complementary metal oxide semiconductor technology node, threshold voltage control and equivalent oxide thickness (EOT) scaling remain concerns for future devices. Therefore, the authors explored the effect of incorporating dysprosium in the gate stack. Results suggest that improved EOT-leakage scaling is possible by adding Dy to the interfacial SiO2 layer in a 1:1 ratio or by adding 10% Dy to bulk HfO2. The deposition of a 1 nm Dy2O3 cap layer lowered the threshold voltage by similar to 250 mV. In addition, for future dynamic random access memory capacitor applications, dielectrics with epsilon of 50-130 are projected by the International Technology Roadmap for Semiconductors, unachievable with standard high-k dielectrics. Theoretical modeling can help direct the experimental work needed for extensive screening of alternative dielectrics. Moreover, materials such as perovskites only exhibit a sufficiently high-k value when properly crystallized. Therefore, control over the crystalline phase of the material might become a necessity to obtain the proper material characteristics as shown for SrTiOx. After crystallization, the permittivity was observed to increase from 20 to 135. In addition, material and gate stack optimization to limit leakage current densities for these higher-k dielectrics will be needed. (C) 2009 American Vacuum Society. [DOI: 10.1116/1.3025855]