Image placement and overlay error specifications in the International Technology Roadmap for Semiconductors continue to get tighter with each successive technology node. Some of the primary contributors to this error in extreme ultraviolet lithography are reticle and chuck surface nonflatness and chucking flatness nonuniformity. In this article, the authors report on results from a set of experiments that were designed to identify and separate chuck and mask contributions to image placement error (IPE). In the first set of experiments, a reticle with large peak-to-valley (P-V) nonflatness was printed to study reticle flattening and reticle thickness variation contributions to the final IPE. The experiments were designed to partition the total IPE into tool correctable and noncorrectable components. A second set of experiments was performed with a flat reticle that can be imaged in four different orientations (0 degrees, 90 degrees, 180 degrees, and 270 degrees). Both reticles have arrays of image placement fiducials that can be printed on the wafer and then used to measure the IPE.