A critical issue associated with the implementation of wafer-level three-dimensional (3D) integration is to achieve excellent bonding and thinning performance without degrading mechanical and electrical characteristics of integrated circuit (IC) chips in the 3D wafer stack. In this work, some mechanical and electrical impacts of wafer bonding and thinning processes used to fabricate 3D ICs are evaluated using patterned wafers with two-level copper interconnect test structures that included either silicon dioxide or porous low-k interlevel dielectrics (ILDs). Benzocyclobutene (BCB) (Cyclotene 3022-35 from Dow Chemical) is the adhesive used, and thinning consists of grinding, chemical mechanical polishing, and wet etching. Three procedures used to evaluate the integrity of BCB bonded and thinned wafer stacks are discussed: (i) optical inspection of the bonding interface using glass wafers with a coefficient of thermal expansion that is close to that of silicon wafers in order to check for voids, defects, and uniformity after each bonding and thinning process; (ii) four-point bending tests to quantify bond strength and to identify the weak bond interface, and (iii) electrical tests of the patterned wafers after two bonding and thinning processes and subsequent BCB removal by plasma ashing to expose the contact pads. These procedures evaluated the impacts of processing of wafer stacks without the need for interwafer interconnect processing. Some negative mechanical and electrical impacts were observed for interconnect structures that include a porous low-k ILD, while no significant changes were observed for interconnect structures with oxide ILD. (C) 2008 The Electrochemical Society.