Multi-gate devices for the 32 nm technology node and beyond

Collaert N; De Keersgieter A; Dixit A; Ferain I; Lai LS; Lenoble D; Mercha A; Nackaerts A; Pawlak BJ; Rooyackers R; Schulz T; San KT; Son NJ; Van Dal MJH; Verheyen P; von Arnim K; Witters L; Meyer KD; Biesemans S; Jurczak M

Solid-State Electronics, Vol.52, No.9, 1291-1296, 2008

DOI10.1016/j.sse.2008.04.018 Export Citation

Multi-gate devices for the 32 nm technology node and beyond

Collaert N, De Keersgieter A, Dixit A, Ferain I, Lai LS, Lenoble D, Mercha A, Nackaerts A, Pawlak BJ, Rooyackers R, Schulz T, San KT, Son NJ, Van Dal MJH, Verheyen P, von Arnim K, Witters L, Meyer KD, Biesemans S, Jurczak M

Due to the limited control of the short channel effects, the high junction leakage caused by hand-to-hand tunneling and the dramatically increased V-T Statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on, planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the Suitability of FinFET-based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed. (C) 2008 Elsevier Ltd. All rights reserved.