The minimum operating voltage (V-min) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The V-min, which is governed by SRAM cells, rapidly increases as devices are miniaturized due to the ever-larger variations in the threshold voltage (V-T) of MOSFETs. The V-min, however, is reduced to the sub-1-V region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k metal gates) that can reduce V-T variations. (C) 2009 Elsevier Ltd. All rights reserved.