At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted trigate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263-5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110-1 [1,2]]. In addition, their undoped channels allow a substantial reduction of the threshold voltage (V-T) mismatch, which makes the MuGFET an excellent candidate for replacing planar MOSFETs in SRAM structures. However, as the Si fin width (W-fin) and gate length (L-g) are down-scaled in order to improve the SCE control and current drive, respectively, the gate work function and access resistance (R-SD) engineering become more challenging. In this paper, two approaches for optimizing the performance of narrow MuGFETs are reported and analysed: the first one relies on the thickness of their Plasma-Enhanced-ALD (PE-ALD) TiN gate electrode. It is demonstrated that very thin PE-ALD TiN gate electrodes allow improved SCE control and enhanced performance in nMOS MuGFETs. The second approach relies on non-amorphizing ion (boron) implantations for both extension and HDD implantations. A substantial R-SD reduction is demonstrated for pMOS MuGFETs with Si fin widths down to 10 run. (C) 2009 Elsevier Ltd. All rights reserved.