Selective epitaxial growth (SEG) of Si1-xGex layers on patterned substrates containing isolated, grouped and global chips has been investigated. The interaction between chips on a wafer was studied, and the results are explained by kinetic gas theory for CVD techniques. A test pattern was designed with a series of grouped chips to calibrate the pattern dependency of SEG (both growth rate and Ge content). The amount of exposed Si coverage on chips in the test pattern ranged between 0.05 and 37%. The layer profile of the calibration pattern was compared to profiles on wafers having a global chip design. A model was developed to estimate the Ge content on substrates with a global design. (C) 2009 Elsevier Ltd. All rights reserved.