This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and I-on/I-off characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the BTB source junction could act as an optimized performance Tunnel FET enabling the cancellation of the drain threshold voltage. To implement a real device, we demonstrate using GAA Si NW with asymmetric strain profile using two local stressor technologies to have >4-5 GPa peak of lateral uniaxial tensile stress in the Si NW. (C) 2010 Elsevier Ltd. All rights reserved.