Transport mechanisms through SiO2/HfO2 gate stacks have been investigated by means of Capacitance-Voltage (C-V), Current-Voltage (I-V) in a large range of temperature (80-400 K) and Transmission Electron Microscopy (TEM) measurements, on several nMOS transistors featuring different interfacial layer and HfO2 thicknesses. The temperature dependency of experimental gate leakage currents have been found to be very weak when plotted versus total charge, except on thicker stacks, in inversion regime, between 300 and 400K. Experiments have been compared with Direct Tunneling current (DT) simulations in inversion regime, using as few as possible arbitrary assumptions and fitting parameters. This comparison has shown that ultra-thin interfacial layer differs from pure SiO2 only below 1 nm thickness, confirming previous theoretical works. (C) 2010 Elsevier Ltd. All rights reserved.