In this work, Al/PbZr0.53Ti0.47O3/n(+)-polycrystalline silicon/Y2O3/Si capacitors and field-effect transistors were fabricated. The n(+)-polycrystalline silicon floating gate was used to reduce the depolarization field of the ferroelectric layer. The gate leakage was reduced (1.68x10(-10) A/cm(2) at 5 V) due to the large electron barrier height at the Y2O3/Si interface. The ratio (A(c)/A(f)) of the control gate area A(c) and the floating gate area A(f) was varied from 1 to 0.25. An I-DS-V-GS memory window of 2.97 V was obtained at a sweeping voltage of 9 V with an A(c)/A(f) ratio of 0.25. An A(c)/A(f) area ratio less than 1 was preferred.