In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates 6 degrees off-cut toward (111). Extended defect-free InP layers were obtained in the top region of 100 nm wide trenches. A thin Ge epitaxial layer was used as an intermediate buffer layer between the Si substrate and the InP layer. A Ge buffer was used to reduce the thermal budget for surface clean and to promote double-step formation on the surfaces. Baking the Ge surface in an As ambient improved the InP surface morphology and crystalline quality. InP showed highly selective growth in trenches without nucleation on SiO2. However, strong loading effects were observed at all growth pressures, which induced variation in local growth rates. We found trench orientation dependence of facet and stacking fault formation. More stacking faults and nanotwins originated from the STI sidewalls in [(1) over bar 10] trenches. High quality InP layers were obtained in the top of the trenches along [110]. The stacking faults generated by the dissociation of threading dislocations are trapped at the bottom of the trenches with an aspect ratio greater than 2. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3489355] All rights reserved.