This paper critically reviews the different mechanisms impacting the current-voltage and capacitance voltage characteristics of complementary metal oxide semiconductor (CMOS) compatible p-n junctions. Special attention is given to the influence of high doping density/high electric fields, mechanical stress and the presence of a hetero-junction either at the junction or in the depletion region. The basic mechanisms reported in the literature are checked for their validity for state-of-the-art structures and processing techniques. Critical issues are pointed out and illustrated for advanced CMOS compatible hetero-junctions, where high-field effects, like trap-assisted tunneling (TAT) and band-to-band-tunneling (BTBT) play a prominent role. The presence of an isotype hetero-junction gives rise to frequency dispersion in the depletion layer capacitance, which becomes more pronounced in combination with grown-in or processing-induced defects at the hetero-interface. Finally, the challenges and opportunities for future devices are addressed. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3555103] All rights reserved.