The effects of fin width on the memory windows of nMOS and pMOS FinFET transistors operated in ZRAM mode are investigated as a function of applied back-gate programming bias during the write pulse. The memory window and retention time of ZRAM cells programmed with a back-gate pulse decrease with decreasing fin width, which is a result of the increased electrostatic shielding by the side-gates of the FinFETs. The gate length and fin width dependences of the memory windows obtained for devices programmed via gate-induced drain leakage (GIDL) are also evaluated for potential ZRAM operation. In contrast to back-gate programming, the memory window increases with decreasing fin width for GIDL programming, which is a much more desirable device scaling trend. Retention times of up to several seconds can be observed in ZRAMs programmed by GIDL with ms length pulses. Memory cycling results demonstrate that the GIDL programming conditions used here do not degrade the device significantly. Shorter retention times are typical of excess charge in the ZRAM body, whereas the relatively longer retention times observed here may be attributed to the injection and trapping of charge in the gate and/or buried oxide near the drain. This could point the way towards improved ZRAM retention properties, since processing techniques such as Si implantation can enhance charge trapping in SOI buried oxides, which in turn may increase retention times for shorter write pulses. (C) 2010 Elsevier Ltd. All rights reserved.