Bottom-up fill of interconnect features requires the proper concentrations of critical plating additives, specifically, a suppressor and a plating accelerator. A comprehensive analytical model for the bottom-up plating process is presented. Using a relatively simple and straightforward analysis, the model provides guidelines for specifying the additives concentrations required for achieving defect-free fill. The model accounts for the transport and competitive adsorption of the additives as well as the increase of accelerator coverage at the bottom of the feature due to curvature enhancement. The degree of sidewalls closure is used as a metric for characterizing the fill and is provided as a function of the feature geometry, the additives parameters, and the concentration. The model is valid for features in which neither copper nor accelerator are depleted due to transport limitations, rendering it valid for features less than about 1 mu m in depth. Consequently, the model is quantitatively valid for all dual-damascene level interconnects, but provides only qualitative results for larger features such as through silicon vias. The theoretical predictions are compared to numerical simulations of the process. Excellent agreement is noted, substantiating the model. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3593038] All rights reserved.