Material removal uniformity during chemical mechanical polishing (CMP) for IC fabrication processes such as shallow trench isolation has previously been shown to be affected by nanotopography (NT) of the wafer frontside (pattern surface). NT is the high frequency height variations of the wafer surface within spatial wavelengths from 0.2 to 20 mm. However, the effect of other topography information such as wafer backside NT and the relatively lower frequency wafer shape on CMP have not been addressed sufficiently. In the present work, the effect of wafer geometry of current and advanced generation wafers on CMP material removal uniformity are investigated using numerical simulations of the CMP process. Specifically, a finite-element based mechanics model was developed and used in conjunction with a wear model based on Preston's equation to simulate the material removal process during CMP. The results demonstrate that the impact of backside NT depends on the stiffness of the CMP backplate (carrier). Simulation results also suggest that higher order wafer shape components can affect CMP results. As technology advances it may be important to control frontside and backside NT as well as higher-order wafer shape in order to reduce their contributions to non-uniform material removal during CMP and the associated yield impact on the integrated circuits that will be manufactured on these substrates. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3615988] All rights reserved.