In conducting the operation of the NAND-type flash memory array, program inhibition is performed by self-boosting of the potential of the floating silicon channel. However, the high program voltage substantially affects the adjacent cells sharing either the bit-line (BL) or the word-line (WL), which results in unwanted program operation, i.e., program disturbance, in the vicinity. In this work, the dependence of self-boosting effect of the channel potential on process variables and device dimensions have been investigated by 3-D device simulation. Through a series of simulations, the process parameters and device dimensions were identified that can provide the optimum condition in self-boosting of the channel potential avoiding such disturbance. The self-boosting effect exhibited a local maximum at the channel doping concentration of 6 x 10(17) boron atoms/cm(3) when the Si fin width was 30 nm and the channel length is 100 nm. Also, it is shown that the boosted channel potential displays monotonic increase with channel length, while it decreases monotonically as the silicon fin width becomes thicker at a given channel doping level. The interpretation of these findings utilizes the graphed results with the advanced capacitance model for a FinFET-based nonvolatile flash memory device. (C) 2010 Elsevier B.V. All rights reserved.