| 학회 |
한국고분자학회 |
| 학술대회 |
2017년 가을 (10/11 ~ 10/13, 제주컨벤션센터) |
| 권호 |
42권 2호 |
| 발표분야 |
분자전자 부문위원회 I |
| 제목 |
Large-Area CVD-grown Sub-2V ReS2 Transistors and Logic Gates |
| 초록 |
We demonstrated the fabrication of large-area ReS2 transistors and logic gates composed of a CVD grown multi-layer ReS2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS2 transistors with graphene electrodes decreased dramatically compared with the SiO2-devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm2/Vs and an on/off current ratio exceeding 104. NMOS logic devices were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. |
| 저자 |
Ajjiporn Dathbun1, 김영찬1, 김성찬1, 유영재2, 강문성3, 이창구1, 조정호1
|
| 소속 |
1성균관대, 2한국화학(연), 3숭실대 |
| 키워드 |
ReS2; chemical vapor deposition (CVD); transistor; large area; logic gate
|
| E-Mail |
|
