| 학회 |
한국화학공학회 |
| 학술대회 |
2008년 봄 (04/23 ~ 04/25, 제주ICC) |
| 권호 |
14권 1호, p.1459 |
| 발표분야 |
화학공정안전 |
| 제목 |
Model Checking for Automatic Verification of Safety Instrumented System in Chemical Process Industry |
| 초록 |
An automatic technique is proposed to verify control logics of safety instrumented system (SIS) and to validate the correctness and completeness of fault tree (FT) for safety integrity level (SIL). Model checking method is applied to find the logical errors of SIS automatically which is difficult to find manually, and to verify them. It is also useful when analyzing FT of SIS. It attempts to validate the correctness and completeness of FT for the SIS. The idea of the verification of FT is to systematically specify the system model and to prove the correctness and completeness of FT. The strength of this method is to synthesize a feasible sequence through a counter-example and to verify its correctness using computation tree logic (CTL) simultaneously. The counter-example consists of a scenario in which the model behaves in an undesired way. Thus the counter-example provides evidence that the model is faulty and needs to be revised. This paper addresses an automatic technique to provide and to modify the P&ID design and the FT of the SIS control logics in the chemical process industry, and presents how model checking approach can be used efficiently in the verification of SIS. |
| 저자 |
김진경1, 이영희1, 권혁면2, 문 일1
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| 소속 |
1연세대, 2산업안전관리공단 |
| 키워드 |
Model checking; Automatic verification; SIS; FT
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| E-Mail |
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| VOD |
VOD 보기 |
| 원문파일 |
초록 보기 |
