| 학회 | 한국재료학회 |
| 학술대회 | 2008년 봄 (05/22 ~ 05/23, 상록리조트) |
| 권호 | 14권 1호 |
| 발표분야 | 반도체재료 |
| 제목 | Design of 45 nm Silicon-on-insulator (SOI) n-metal―oxide―semiconductor Field-effect Transistor (MOSFET) Floating Body Cell (FBC) for Optimal Memory Characteristics |
| 초록 | As the design rule goes to less than 60 nm, the size of a capacitor can not be smaller than that which is needed for maintaining the existing capacitance of dynamic random-access memory (DRAM), there is also major difficulty in the usage of DRAM as a memory because of the significant increase of storage node leakage caused by high electric field of cell area. Additionally the manufacturing of a capacitor with a complex structure is the biggest impediment in the fabrication of DRAM cell. The flash memory has a significant advantage of having non-volatile feature but because of the grain size non-uniformity of poly-silicon floating gate which is used as a storage node, it is difficult to scale down for the size of 32 nm or less. To overcome these limitations, several memory cells have been suggested. One of those is floating body cell (FBC) which has the structure of silicon-on-insulator (SOI). In partially depleted SOI (PD), holes which generated by impact ionization are unable to escape and eventually accumulated on the buried oxide, in which case what is called the “floating body effect” occurs. This causes the change of VT of MOSFET and by reading the change of VT we can use it as a memory which has 'write (0)' and 'write (1)' states. Because FBC uses SOI substrate, low-power, high performance operation and the pattern limit(~ 10 nm) process of lithography can be realized. By virtue of these benefits, FBC has been known as a influential memory cell which can be a substitute for DRAM. In our research, we optimized the cell structure of 45 nm FBC for the purpose of optimal memory feature. Depending on the interface trap density of buried oxide, the top silicon and buried oxide thickness dependency, the optimal conditions were investigated and the characteristics of memory were observed. As a result, the lower the value of Dit the longer the retention time and we observed that the most excellent memory characteristics is shown when the top silicon thickness of the FBC operates in between the mode of fully depletion and partially depletion. For the gate dielectric materials, SiO2 single film and the laminating structure of HfO2 and Al2O3 layers have been comparatively studied. And in conclusion, by controlling of dimensional parameter and the process variables, we could propose the optical FBC structure with the wide on/off VT margin and the improved retention time. *This work was supported by Brain Korea 21 project in 2008. |
| 저자 | Jin-Woo Choi1, Young-Hwan Ryu2, Seong-Je Kim1, Tae-Hun Shim2, Jea-Gun Park1 |
| 소속 | 1Nano SOI Process Laboratory, 2Hanyang Univ. |
| 키워드 | Cap-less DRAM; retention; VT margin |
