| 학회 |
한국화학공학회 |
| 학술대회 |
2015년 봄 (04/22 ~ 04/24, 제주 ICC) |
| 권호 |
21권 1호, p.160 |
| 발표분야 |
공정시스템 |
| 제목 |
Lead-Lag Compensators for Higher Order SISO Dead-Time System: Time Domain Approach |
| 초록 |
A simplified algorithm for designing a lead-lag compensator in time domain is proposed in this paper. The lead-lag compensator is designed in order to satisfy the control specifications in time domain such as damping ratio, maximum overshoot settling time and steady sate error. Using the correlation between frequency and time domain, the algorithm can also be used to solve the required compensator in the case the design specifications are given in time domain, such as phase margin and gain margin. The other finding of this research is a new Proportional Derivative (PD) compensator that is obtained after an artistic modification of the designed lead-lag compensator, herein called fortunate compensator. The proposed algorithm make it possible and easily handle the design of PI, PD and PID controller that satisfy time response or frequency response specifications. This work was supported by Basic Science Research Program through the NRF funded by the Ministry of Education, Science and Technology (2012012532). This work was also supported by Priority Research Centers Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (2014R1A6A1031189). |
| 저자 |
이문용1, 로드릭참나1, 윤일준2, 김서은1, Riezqa Andika1
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| 소속 |
1영남대, 2경상대 |
| 키워드 |
lead-lag compensator; lead compensator; lag compensator; dead time system
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| E-Mail |
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| 원문파일 |
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