검색결과 : 6건
| No. | Article |
|---|---|
| 1 |
Dependence on an oxide trap's location of random telegraph noise (RTN) in GIDL current of n-MOSFET Gia QN, Yoo SW, Lee H, Shin H Solid-State Electronics, 92, 20, 2014 |
| 2 |
Characterization and optimization of partially depleted SOI MOSFETs for high power RF switch applications Im D, Lee K Solid-State Electronics, 90, 94, 2013 |
| 3 |
Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL) Cho S, Lee JH, O'uchi S, Endo K, Masahara M, Park BG Solid-State Electronics, 54(10), 1060, 2010 |
| 4 |
Effects of fin width on memory windows in FinFET ZRAMs Zhang EX, Fleetwood DM, Alles ML, Schrimpf RD, Mamouni FE, Xiong W, Cristoloveanu S Solid-State Electronics, 54(10), 1155, 2010 |
| 5 |
Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster Ishigaki T, Tsuchiya R, Morita Y, Yoshimoto H, Sugii N, Iwamatsu T, Oda H, Inoue Y, Ohtou T, Hiramoto T, Kimura S Solid-State Electronics, 53(7), 717, 2009 |
| 6 |
Effect of Ti-rich TiN as a Co-salicide capping layer for 0.15 um embedded flash memory devices and beyond Kim NS, Mukhopadhyay M, Wong WY, You YS, Zhao J, Lim B, Lee KS, Shukla D, Goh IS Thin Solid Films, 504(1-2), 20, 2006 |