검색결과 : 21건
| No. | Article |
|---|---|
| 1 |
Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements Pradeep K, Poiroux T, Scheer P, Juge A, Gouget G, Ghibaudo G Solid-State Electronics, 145, 19, 2018 |
| 2 |
Characterization and modelling of layout effects in SiGe channel pMOSFETs from 14 nm UTBB FDSOI technology Berthelon R, Andrieu F, Ortolland S, Nicolas R, Poiroux T, Baylac E, Dutartre D, Josse E, Claverie A, Haond M Solid-State Electronics, 128, 72, 2017 |
| 3 |
Trigate nanowire MOSFETs analog figures of merit Kilchytska V, Makovejev S, Barraud S, Poiroux T, Raskin JP, Flandre D Solid-State Electronics, 112, 78, 2015 |
| 4 |
Extra-low parasitic gate-to-contacts capacitance architecture for sub-14 nm transistor nodes Niebojewski H, Le Royer C, Morand Y, Rozeau O, Jaud MA, Dubois E, Poiroux T, Bensahel D Solid-State Electronics, 97, 45, 2014 |
| 5 |
Scaling of Trigate nanowire (NW) MOSFETs to sub-7 nm width: to Single Electron Transistor Deshpande V, Barraud S, Jehl X, Wacquez R, Vinet M, Coquand R, Roche B, Voisin B, Triozon F, Vizioz C, Tosti L, Previtali B, Perreau P, Poiroux T, Sanquer M, Faynot O Solid-State Electronics, 84, 179, 2013 |
| 6 |
Influence of device architecture on junction leakage in low-temperature process FDSOI MOSFETs Sklenard B, Batude P, Rafhay Q, Martin-Bragado I, Xu CQ, Previtali B, Colombeau B, Khaja FA, Cristoloveanu S, Rivallin P, Tavernier C, Poiroux T Solid-State Electronics, 88, 9, 2013 |
| 7 |
Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology Fenouillet-Beranger C, Perreau P, Benoist T, Richier C, Haendler S, Pradelle J, Bustos J, Brun P, Tosti L, Weber O, Andrieu F, Orlando B, Pellissier-Tanon D, Abbate F, Richard C, Beneyton R, Gregoire M, Ducote J, Gouraud P, Margain A, Borowiak C, Bianchini R, Planes N, Gourvest E, Bourdelle KK, Nguyen BY, Poiroux T, Skotnicki T, Faynot O, Boeuf F Solid-State Electronics, 88, 15, 2013 |
| 8 |
Scaling of high-kappa/metal-gate TriGate SOI nanowire transistors down to 10 nm width Coquand R, Barraud S, Casse M, Leroux P, Vizioz C, Comboroure C, Perreau P, Ernst E, Samson MP, Maffini-Alvaro V, Tabone C, Barnola S, Munteanu D, Ghibaudo G, Monfray S, Boeuf F, Poiroux T Solid-State Electronics, 88, 32, 2013 |
| 9 |
Transistors on hybrid UTBB/Bulk substrates fabricated by local internal BOX dissolution Nguyen P, Andrieu F, Casse M, Tabone C, Perreau P, Lafond D, Dansas H, Tosti L, Veytizou C, Landru D, Kononchuk O, Guiot E, Nguyen BY, Faynot O, Poiroux T Solid-State Electronics, 90, 39, 2013 |
| 10 |
Study of substrate orientations impact on Ultra Thin Buried Oxide (UTBOX) FDSOI High-K Metal gate technology performances Ben Akkez I, Fenouillet-Beranger C, Cros A, Perreau P, Haendler S, Weber O, Andrieu F, Pellissier-Tanon D, Abbate F, Richard C, Beneyton R, Gouraud P, Margain A, Borowiak C, Gourvest E, Bourdelle KK, Nguyen BY, Poiroux T, Skotnicki T, Faynot O, Balestra F, Ghibaudo G, Boeuf F Solid-State Electronics, 90, 143, 2013 |