검색결과 : 1건
| No. | Article |
|---|---|
| 1 |
Design and analysis of different trigger techniques for ESD clamp circuit in 0.5-mu m 5 V/18 V CDMOS process Zhang WJ, Yang L, Wang Y, Jin XL Solid-State Electronics, 135, 8, 2017 |
| No. | Article |
|---|---|
| 1 |
Design and analysis of different trigger techniques for ESD clamp circuit in 0.5-mu m 5 V/18 V CDMOS process Zhang WJ, Yang L, Wang Y, Jin XL Solid-State Electronics, 135, 8, 2017 |