A 0.25 mu m (MOSFET) technology using 6.5 nm thick in situ rapid thermal gate dielectrics, including RTO, RTCVD, and RPECVD was designed for channel length of 0.18 +/- 0.06 mu m and evaluated experimently. Devices with L(eff) down to 0.17 mu m were fabricated using the different dielectrics and electrically characterized. In addition to the RTP dielectrics, the technology features a LOGOS isolation having small bird’s beak (45 nm), very shallow source/drain junction and extension depths (70 and 30 nm, respectively) with very low gate induced drain leakage (GIDL). The key technology elements such as isolation, channel dopant redistribution, polysilicon gate patterning, and shallow junction formation are discussed along with the impact of the different dielectrics on device characteristics.