A self-aligned contact (SAC) technology is developed for the application of electrical contacts between the local interconnect and the silicon diffusion regions for 0.18 mu m static random access memory cells. The key components of this SAC technology include the deposition and gap fill of borophosphosilicate glass (BPSG) films, a selective oxide etch process, and metal-plug contact formation by Ti/TiN-liner silicidation and W filling. The BPSG film, deposited by plasma enhanced chemical vapor deposition, has exhibited an ability of filling 0.04 mu m spaces with an aspect ratio (AR) of about 10:1 after reflow at 800 degrees C. Reduction of the reflow temperature without gap-fill deterioration by increasing the B incorporation in the BPSG film is not feasible due to an increase of BPSG defects. The oxide SAC etch performance is modulated by an oxide-to-nitride etch selectivity which has shown a strong dependence on the wafer temperature. The etch process window is improved by optimization of the process conditions including the wafer temperature uniformity. A novel SAC etch process was demonstrated for an similar to 0.2 mu m SAC opening. The electrical performance of a contact with an AR as high as 10:1 has met the design requirement, which has indicated sufficient liner silicidation and an excellent W plug process. Investigation of the contact resistance dependence on the contact AR has shown a reduction in contact resistance with increasing AR. All these findings are very instructive for our development projects.