The electrical performance of hydrogen silsesquioxane (HSQ) as the interlayer level dielectric (ILD) has been determined by using two-metal-layered test structures to study the impact of oxide liner thickness on the capacitance reduction. In comparison with SiO2, HSQ test structures formed with SiO2 cap and liner or with SiO2 cap only, have 20-27% lower intraline capacitance while 6-16% reduction was observed for fluorosilicate glass (FSG) relative to SiO2. It was found that the capacitance of SiO2/HSQ ILDs did not vary with oxide liner thickness as expected. Similar effects were observed with via resistance measurement. Analysis of the structure shows that wide variation of SiO2/HSQ/SiO2 stack thickness after oxide Chemical Mechanical Polishing (CMP) step changed the expected contribution of liner thickness on the intraline and interlayer capacitance. This thickness variation also has a strong impact on landed/unlanded via resistance. Therefore, a good control of oxide CMP on the ILD stack is needed to reduce the thickness variation of the liner/HSQ/cap ILD stack which in turn will enhance process yields in the 0.18 mum devices.