화학공학소재연구정보센터
Solid-State Electronics, Vol.47, No.7, 1199-1203, 2003
Design considerations for fully depleted SOI transistors in the 25-50 nm gate length regime
Drift-diffusion simulations have been carried out to investigate the design space for n-channel fully depleted (FD) SOI transistors with undoped channels and midgap gates in the 25-50 nm gate length regime. Gate length, Si-body thickness, source drain doping concentration profile, and spacer width have been varied. Provided that the gate length is larger than 3-4 times the Si-body thickness, we find that the high performance targets of the International Technology Roadmap for Semiconductors can be fulfilled for many different parameter combinations. This means that FD SOI is a suitable technology for devices with feature sizes on this length scale. (C) 2003 Elsevier Science Ltd. All rights reserved.