| 1 |
Experimental observation of zero DIBL in short-channel hysteresis-free ferroelectric-gated FinFET
Shin J, Shin C
Solid-State Electronics, 153, 12, 2019 |
| 2 |
Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell
Xu ZZ, Liu DH, Hu J, Chen WJ, Qian WS, Kong WR, Zou SC
Solid-State Electronics, 152, 46, 2019 |
| 3 |
Improvement in drain-induced-barrier-lowering and on-state current characteristics of bulk Si fin field-effect-transistors using high temperature Phosphorus extension ion implantation
Kikuchi Y, Hopf T, Mannaert G, Everaert JL, Kubicek S, Eyben P, Waite A, Borniquel JID, Variam N, Mocuta D, Horiguchi N
Solid-State Electronics, 152, 58, 2019 |
| 4 |
A unified analytical drain current model for Double-Gate Junctionless Field-Effect Transistors including short channel effects
Raksharam, Dutta AK
Solid-State Electronics, 130, 33, 2017 |
| 5 |
A novel scaling theory for fully depleted pi-gate (Pi G) MOSFETs
Chiang TK
Solid-State Electronics, 103, 199, 2015 |
| 6 |
Revisited parameter extraction methodology for electrical characterization of junctionless transistors
Jeon DY, Park SJ, Mouis M, Berthome M, Barraud S, Kim GT, Ghibaudo G
Solid-State Electronics, 90, 86, 2013 |
| 7 |
Threshold voltage, and 2D potential modeling within short-channel junctionless DG MOSFETs in subthreshold region
Holtij T, Schwarz M, Kloes A, Iniguez B
Solid-State Electronics, 90, 107, 2013 |
| 8 |
Electrical characteristics of 20-nm junctionless Si nanowire transistors
Park CH, Ko MD, Kim KH, Baek RH, Sohn CW, Baek CK, Park S, Deen MJ, Jeong YH, Lee JS
Solid-State Electronics, 73, 7, 2012 |
| 9 |
Physical simulation of drain-induced barrier lowering effect in SiC MESFETs
Zhu CL, Rusli, Almira J, Tin CC, Yoon SF, Ahn J
Materials Science Forum, 483, 849, 2005 |
| 10 |
Scaling of lowered source/drain (LSD) and raised source/drain (RSD) ultra-thin body (UTB) SOI MOSFETs
An X, Huang R, Zhang X, Wang YY
Solid-State Electronics, 49(3), 479, 2005 |
