검색결과 : 14건
| No. | Article |
|---|---|
| 1 |
GIDL analysis of the process variation effect in gate-all-around nanowire FET Kim S, Seo Y, Lee J, Kang M, Shin H Solid-State Electronics, 140, 59, 2018 |
| 2 |
Design strategies for ultra-low power 10 nm FinFETs Walke A, Schlenvogt G, Kurinec S Solid-State Electronics, 136, 75, 2017 |
| 3 |
Dependence on an oxide trap's location of random telegraph noise (RTN) in GIDL current of n-MOSFET Gia QN, Yoo SW, Lee H, Shin H Solid-State Electronics, 92, 20, 2014 |
| 4 |
Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications Sasaki KRA, Nicoletti T, Almeida LM, dos Santos SD, Nissimoff A, Aoulaiche M, Simoen E, Claeys C, Martino JA Solid-State Electronics, 97, 30, 2014 |
| 5 |
Characterization and optimization of partially depleted SOI MOSFETs for high power RF switch applications Im D, Lee K Solid-State Electronics, 90, 94, 2013 |
| 6 |
A study on the performance of metal-oxide-semiconductor-field-effect-transistors with asymmetric junction doping structure Park H, Choi B Current Applied Physics, 12(6), 1503, 2012 |
| 7 |
GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics Galeti M, Rodrigues M, Martino JA, Collaert N, Simoen E, Claeys C Solid-State Electronics, 70, 44, 2012 |
| 8 |
Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL) Cho S, Lee JH, O'uchi S, Endo K, Masahara M, Park BG Solid-State Electronics, 54(10), 1060, 2010 |
| 9 |
Effects of fin width on memory windows in FinFET ZRAMs Zhang EX, Fleetwood DM, Alles ML, Schrimpf RD, Mamouni FE, Xiong W, Cristoloveanu S Solid-State Electronics, 54(10), 1155, 2010 |
| 10 |
Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster Ishigaki T, Tsuchiya R, Morita Y, Yoshimoto H, Sugii N, Iwamatsu T, Oda H, Inoue Y, Ohtou T, Hiramoto T, Kimura S Solid-State Electronics, 53(7), 717, 2009 |