검색결과 : 7건
| No. | Article |
|---|---|
| 1 |
Influence of crystal orientation and body doping on trigate transistor performance Landgraf E, Rosner W, Stadele M, Dreeskornfeld L, Hartwich J, Hofmann F, Kretz J, Lutz T, Luyken RJ, Schulz T, Specht M, Risch L Solid-State Electronics, 50(1), 38, 2006 |
| 2 |
Charge trapping memory structures with Al2O3 trapping dielectric for high-temperature applications Specht M, Reisinger H, Hofmann F, Schulz T, Landgraf E, Luyken RJ, Rosner W, Grieb M, Risch L Solid-State Electronics, 49(5), 716, 2005 |
| 3 |
NVM based on FinFET device structures Hofmann F, Specht M, Dorda U, Kommling R, Dreeskornfeld L, Kretz J, Stadele M, Rosner W, Risch L Solid-State Electronics, 49(11), 1799, 2005 |
| 4 |
Impact of technology parameters on device performance of UTB-SOI CMOS Schulz T, Pacha C, Luyken RJ, Stadele M, Hartwich J, Dreeskornfeld L, Landgraf E, Kretz J, Rosner W, Specht M, Hofmann F, Risch L Solid-State Electronics, 48(4), 521, 2004 |
| 5 |
Nanoscale FinFETs for low power applications Rosner W, Landgraf E, Kretz J, Dreeskornfeld L, Schafer H, Stadele M, Schulz T, Hofmann F, Luyken RJ, Specht M, Hartwich J, Pamler W, Risch L Solid-State Electronics, 48(10-11), 1819, 2004 |
| 6 |
Design considerations for fully depleted SOI transistors in the 25-50 nm gate length regime Luyken RJ, Schulz T, Hartwich J, Dreeskornfeld L, Stadele M, Rosner W Solid-State Electronics, 47(7), 1199, 2003 |
| 7 |
Planar and vertical double gate concepts Schulz T, Rosner W, Landgraf E, Risch L, Langmann U Solid-State Electronics, 46(7), 985, 2002 |